SIMULATION OF NOVEL 9-LEVEL INVERTER TOPOLOGY WITH REDUCED NUMBER OF SWITCHES
Journal: International Journal of Electrical Engineering and Technology (IJEET) (Vol.11, No. 3)Publication Date: 2020-05-31
Authors : Palanisamy R Shubhra Shekhar Dey Arpit Rana D. Karthikeyan D. Selvabharathi;
Page : 58-65
Keywords : Multilevel inverter; cascaded H-bridgeiinverter; Sine Pulse Width Modulation (SPWM); Total Harmonic Distortion.;
Abstract
This paper presents a new circuitry for multilevel inverter which was designed by using less number of DC sources(4 batteries). Also the number of switches were reduced and IGBT were used as switches. The design is a modification of cascaded HBridgeiMultilevel inverter. The steps in the output wave follow the equation 2k+1, where k is the number of DC sources. Since the number of steps is increased, the resemblance of the output waveform to the sinusoidal wave is also increased, thereby increasing the efficiency of the system, as compared to the previous models of multilevel inverter. 9 level voltage output is obtained from 4 DC sources. As the number of swtiches are reduced, the dV/dt losses, and harmonic distortions are also reduced. The experimental setup is validated using a simpleiresistive load.
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Last modified: 2021-03-03 17:01:27