FUTURE OF TIMING ANALYSIS IN VLSI CIRCUITS

As the VLSI technology scales down into the nanometer domain, the on-chip variations have become more unpredictable. They require a more detailed modelling and analysis of Process, Voltage and Temperature corners of the design. These variations which did not have a pronounced effect on larger chips, have now become inevitably significant and cannot be ignored. This paper presents an overview of the existing Timing Analysis methods and identifies their drawbacks. The need for an integrated Timing Analysis tool which has features to model all the on-chip variations is discussed. By employing a PVT aware Timing Analysis tool, the verification engineer can achieve faster timing closure while not compromising on the quality of results.