DESIGN & IMPLEMENTATION OF RECONFIGURABLE ADAPTIVE FAULT TOLERANT SYSTEM FOR ALU

This paper presents the design of reconfigurable adaptive fault tolerant system for 32 bit ALU. In electronic industry, billions of components are built in a single VLSI chip. If the testing cost is reduced to small amount then there will be a benefit of huge amount to produce large number of VLSI circuits. This implemented 32 bit ALU addresses the low power, area efficient with less delay. One of the fundamental issues joined with the plan of FT frameworks incorporate shortcoming/mistake location and fix during framework activity, to take the framework back to the state wherein it works effectively. To handle these issues, with the plan of the FT frameworks, the idea of online checkers and excess must be consolidated. In this paper have designed 32 bit Arithmetic Logic Unit (ALU) using various hardware redundancy techniques with partial dynamic reconfiguration and fault coverage achieved 100%.