AN EFFICIENT TCAM DESIGN USING MULTICASCADING TECHNIQUE

Ternary content-addressable memories are an essential part of network routers. The space requirements of TCAM applications are increasing every day. Current solutions of TCAMs are affected by inefficiency in the storage space. The multicascading technique used for SRAM in this design achieves an effective storage use. Existing SRAM designs diminish the effect of the addition in the conventional TCAM pattern width from a sharp increase in memory utilization to a gradual one by using a cascaded configuration of block RAMs (BRAMs). But the BRAMs on the even the most advanced FPGAs have a limit in terms of minimum depth, which in turn affects the storage efficiency for the TCAM bits. Our proposed design circumvents this limit by mapping the divisions in the conventional TCAM table to sub blocks, which are not very deep. of the configured BRAMs, thus attaining an efficient memory design. The proposed design uses the configured two ported BRAMs of the design as a multiple port memory using the unique technique called as multicascading. This technique is implemented by clocking the block with a higher internal clock which is a multiple of the system clock, to access the various sub blocks of the block RAM in a single system cycle. Our design implemented in Xilinx ISE achieves better memory utilization, lower delay as well as lower power consumption with the increase in memory implementation size.