Low Power Implementation of Fast Fourier Transform Processor on FPGA

DFT(Discrete Fourier Transform) is a fundamental principle of DSP whose applications vary from Spectral analysis, Data compression, solving Partial Differential Equations, convolution and multiplication of large numbers. Despite its enormous potential in theoretically solving many DSP problems, it is of very little use in practical because of its extremely expensive hardware implementation. It is due to its complexity O(N2), N being number of data points. To address this problem Fast Fourier Transform (FFT) was introduced. This algorithm uses the symmetry and periodicity properties of Twiddle Factor involved with DFT to reduce the number of calculations drastically. For N=1024, FFT is more than 200 times faster than DFT. In this paper we focus on implementing FFT for a processor, by applying Cooley-Tukey Algorithm to improve the speed of computation at expense of minimum power. This paper discusses in detail about the core FFT block and auxiliary blocks of Testbench like Buffer Ram, Complex Multiplier and Bit Shifter. The simulation has been done in Xilinx ISE with verification on two different FPGA platforms. The correctness of our algorithm is demonstrated via output waveforms.