Energy Aware FSM Based Architecture for Matching of Data Encoded With ErrorCorrecting Codes: Survey

A new architecture for matching the data protected with an error-correcting code (ECC) is presented in this brief to reduce latency and complexity. In this paper, by making use of the property that soft errors are rare and hard errors increase gradually with the number of writes, a novel scheme is proposed to correct both soft and hard errors through integrating 2-error-correcting BCH codes and ECPs (error-correcting pointers). In particular, we propose an efficient technique for partial self-checking FINITE STATE MACHINES (FSM) design based on on-line monitoring of FSM state transitions.