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32-Bit RISC and DSP System Design in an FPGA?

Journal: International Journal of Computer Science and Mobile Computing - IJCSMC (Vol.3, No. 12)

Publication Date:

Authors : ; ;

Page : 361-368

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Reduced Instruction Set Computer (RISC) cores use fewer instructions with simple constructs, and therefore they can be executed much faster within the CPU without having to use memory as often. When combined with a digital signal processor system (DSP), they can perform several operations quickly and efficiently. Here, the project present a system with RISC and DSP that uses very high-density logic (VHDL) and a field-programmable gate array (FPGA) to improve speed and functionality. This offers a variety of features, including arithmetic operations and Fourier transform. The design will be useful in several areas, including Android phones.

Last modified: 2014-12-23 01:32:56