Comparative Analysis of CMOS Comparator for A-D Converter at 1um and 45 nm Technology Nodes
Journal: International Journal of Science and Research (IJSR) (Vol.6, No. 2)Publication Date: 2017-02-05
Authors : M. Nizamuddin;
Page : 1658-1662
Keywords : Comparator; ADC; Low Power; CMOS; Simulation; Design;
Abstract
In Analog to digital convertor design converter, high speed comparator influences the overall performance of Analog to Digital Converter (ADC) directly. This paper presents the CMOS comparator for effective ADC at low power dissipation. A schematic design of this comparator is given with 1m Technology and simulated in HSPICE. Simulation results are presented and the design has DC Gain of 68dB, power dissipation of 1.25 mW at 5 V for 1um and the design has DC Gain of 18dB, power dissipation of 325 mW at 1.2V for 45 nm using HSPICE software.
Other Latest Articles
- Design of One Stage Operational Transconductance Amplifiers at 65nm and 90 nm for Low Power Applications
- Exhaust Emission Control by Using Coppler Plate and Ammonia Solution
- Variation of Bulk Density and WHC of Vermicompost Exposed to Selective Commercial Fertilizers
- Performance Analysis of Regularized Adaptive Filter for an Acoustic Echo Cancellation Application
- Nanotechnology for Advancement in Transportation Engineering
Last modified: 2021-06-30 17:48:27