Area-Efficient and High Speed Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. The basic work is a simple and efficient gate-level modification to significantly reduce the area, delay and power of the CSLA. Based on this modification 16-bit CSLA architecture have been developed and compared with the existing regular and modified CSLA architecture. The proposed design has reduced area, delay and power as compared with the existing modified CSLA. This work estimates the performance of the proposed designs in terms of delay, area, power, and their products are implemented in Xilinx FPGA.