”A review of Power Efficient Carry Select Adder”

Abstract? Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Conventional carry-select adder (CSL) is still area-consuming due to the dual ripple carry adder structure. The excessive area overhead makes CSL relatively unattractive but this has been circumvented by the use of add-one circuit introduced recently. The logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter BEC based CSLA are analyzed to study the data dependence and to identify redundant logic operations. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. They have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. Experimental analysis shows that this architecture achieves the three folded advantages in terms of area, delay and power.