Review of low-power double-tail comparator using different design

Abstract? the need for low-power, area efficient and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In order to achieve high-speed of comparator, to compensate the reduction of the supply voltages the larger transistors are required, which also means that more die area and power is needed. On the basis of the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. The double-tail topology can operate faster and can be used in lower supply voltages, while consuming nearly the same power as the conventional dynamic comparator. Since, designing of double-tail comparator will give the better performance and optimized the power performance according to the CMOS technology used and the circuit operates on high-speed. They are commonly used in devices that measure and digitize analog signals, such as analog-to-digital converters (ADCs), as well as relaxation oscillators.