Design and Analysis of Double Precision Floating Point Division Operator Based on CORDIC Algorithm

Floating point arithmetic units provides better accuracy, precision and it covers larger data ranges compared to fixed point. Designing of floating point division operator is complex compared to other data operands. In general, division operation based on CORDIC algorithm has a limitation in term of the range of inputs that can be processed by the CORDIC machine to give proper convergence and precise division operation result. This paper involves the design of Double precision floating point division operator using CORDIC algorithm. The new architecture of CORDIC Algorithm is proposed in this project which overcomes the limitation in terms of range of inputs and is capable of processing broader input ranges. The performance is evaluated for large input tests. The results show that the proposed system gives precise division operation results with broader input ranges. The proposed hardware architecture is modeled in VERILOG and synthesized on Virtex-4 FPGA device (xc4vsx25). The design has achieved maximum frequency of 211.879MHz.