A Survey on an VLSI Based Data Transfer Schemes

Packet data transfer scheme is introduced for intra chip data transfer to solve an interconnection problem. Double transmission lines are provided as a platform of the micronetwork. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. An application to a parallel VLSI processor is also discussed. In comparison with a multi-bus architecture the parallelism can be greatly increased under the same chip size because of the compactness of the micronetwork. Also a new packet data transfer scheme has been introduce (PDTS) is introduced to reduce the configuration control memory size of a multiple valued dynamic reconfigurable VLSI based on a logic memory architecture In PDTS the CCM size of the memory is proportional not to the no of the distributed memory modules in the reconfigurable Very Large Scale Integration but to the no of read operations in all the memories. Thus remarkable reduction of the CCM size can be achieved in comparison to the conventional control scheme. Moreover the PDTS contributes to fine grain ON/OFF control of current sources in Differential pair circuits (DPCS) utilizing flag information which indicates whether the data is valid or not.