MULTIPLE FAULT DIAGNOSIS FOR HIGH SPEED HYBRID MEMORY ARCHITECTURE

This paper presents a built-in self-test (BIST)-based scheme for fault diagnosis that can be used to identify permanent failures and automatic correction in all memories & circuits. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects.