Implementation, Simulation and Synthesis of RSA Cryptosystem

In this paper, we present a methodology to develop 64-bit RSA encryption engine on FPGA that can be used as a standard device in the secured communication system. The RSA algorithm has three parts i. e. key generation, encryption and decryption. The algorithm also requires random prime numbers for processing and generation of public and private key. We use right-to-left-binary method for the exponent calculation. This reduces the number of cycles enhancing the performance of the system and reducing the area usage of the FPGA. These blocks are coded in Verilog and are synthesized using Cadence RC Compiler tool and simulated in ModelSim-Altera Student Edition.