Review on Different Types of Power Efficient Adiabatic Logics

This paper shows a new adiabatic approach known as Positive Feedback Adiabatic Logic. Adiabatic circuits and static CMOS logic are used in low power VLSI chips to achieve improved device performance. Power reduction is achieved by recovering the energy in the recovery phase of the power clock. The power saving in the adiabatic logic over static CMOS logic can reach more than 90 %. The main goal of this paper is to provide low power solutions to VLSI designers. The dynamic power requirement of CMOS circuits is a major concern in the design of personal information systems and large computers. The clocking schemes and signal waveforms are different from those of standard CMOS circuits. Adiabatic logic provides a way to reuse the energy stored in load capacitors rather than the conventional way of discharging the load capacitors to the ground and wasting this energy.