Design of CMOS Tapered Buffer for High Speed and Low Power Applications using 65nm Technology

This paper describes the power dissipation and propagation delay issues in CMOS buffer circuits while driving large capacitive loads which are often presents in CMOS IC-s and proposes a CMOS buffer design for minimizing power dissipation and propagation delay. The reduction in power dissipation is achieved by minimizing short circuit power and subthreshold leakage power which is predominant when supply voltage (VDD) and threshold voltage (Vth) are scaled down for low voltage applications. The proposed buffer has been designed and simulated using Tanner SPICE tool in 65 nm VLSI technology. The results show that modified taper buffer design has a substantial amount of decrease in power dissipation.