Design and Analysis of Asynchronous 16*16 Adiabatic Vedic Multiplier Using ECRL and EEAL Logic

In this paper, we describe adiabatic Vedic multiplier using efficient charge recovery logic (ECRL) and energy efficient adiabatic logic (EEAL). In today-s world low power hindrance have become a major important factor in modern VLSI design. Because of the increasingly draconian demands for battery space and weight in portable multimedia devices, energy productive and high yielding circuits are required, particularly in digital multipliers which are basic building blocks of digital signal processors. For speed and power criteria the Urdhva-Tiryagbhayam Vedic multiplier is effective and adiabatic logic style is said to be an attractive solution for low power electronic applications. With adiabatic logic most of the energy is restored to the source instead of dissipating as heat. Proposed work focuses on the design of low power and area-efficient adiabatic Vedic multiplier using TSMC0.18m CMOS process technology in HSPICE G2012.06.