Systematic Approach of Low Power Truncation-Error-Tolerant (TET) Adder

In modern VLSI technology, the presence of all kinds of errors has become unavoidable. By adopting a rising concept in VLSI design and testing, error tolerance (ET), an error-tolerant-adder (ETA) is implemented. The ETA is able to ease the strict restriction on accuracy, and at the same time attain enormous improvements in both the power consumption and speed execution. We can compare it to its ceremonious counterparts, the implemented ETA is able to achieve more than 65 % improvement in the Power-Delay-Product (PDP). There is one advantage of the implemented ETA is that it can tolerate certain amount of errors. This paper compares the performance of the ETA in terms of accuracy, delay and power consumption with that of conventional adders.