Design Of 7T SRAM Cell Using Self-Controllable Voltage Level Circuit to Achieve Low Power

Modern ICs are enormously complicated due to decrease in device size and increase in chip density involving several millions of transistors per chip. The rules for what can and cannot be manufactured leads to a tremendous increase in complexity due to the amount of power dissipation is increased. Power dissipation can be in various forms as dynamic, subthreshold, etc. In this project first, a low power 7T SRAM Cell is designed and later it is build with Self-controllable Voltage level circuit for maintaining low power consumption and high performance. A Self-Controllable Voltage Level (SVL) Circuit can supply a maximum dc voltage when the load circuits are in active mode or it can also decrease the dc voltage supplied to a load circuit which is said to be in standby mode. This SVL circuit can reduce standby leakage power of CMOS logic circuits drastically with minimum chip size and speed by considering 7T as load circuit. Furthermore, it can also be applied to memories and registers, because such circuits using SVL technique can retain data even in the standby mode. The entire simulations have been done on 180nm single n-well CMOS bulk technology, in virtuoso platform of cadence tool with the supply voltage 0.7V and frequency of 25MHz.