Enhanced Way Tagged Cache Design Using Partial Tag Bloom Filter for Low Level (L2) Cache

High-performance microprocessors utilize cache write-through policy for performance improvement, at the same time achieving good tolerance to soft errors in on-chip caches. Write-through policy also consumes large power due to the increased access to caches in different level during write operation. The objective of this paper is to improve the energy efficiency of write-through caches as well as improving the access time with a new cache architecture referred as way tagged cache. Many high performance microprocessor designs have chosen the write-through policy by maintaining the way tags of L2 cache in the L1 cache during read operations, proposed method uses L2 cache to work in an equivalent direct-mapping manner during write hits, which account for the majority of L2 cache accesses. During read operation, the way tag of the L2 cache information is available in L1 cache. In the proposed method, partial tag partially matches the incoming address with the cache line address. If the partial tag gives matches then full tag comparison will be performed. If no match is found, then the cache line (s) is not associated with the incoming address. Due to this the way-tag technique enables L2 cache to work in an equivalent direct mapping manner during write hits when the cache data compared with the input data, and it leads to reduce the significant energy without performance degradation and the access time. While the corresponding way tag information is not available in the way-tag arrays for read misses, therefore all the ways in the L2 cache are activated simultaneously under read misses.