Design of Multimode Deinterleaver for different Wireless Communication Standards

The advancement in communication systems has reached a new level with the development of wireless devices. The data stream to be transferred has to undergo different error correcting techniques to ensure better reliability and security. Interleaving is a basic method to reduce the effect of burst errors. It is mostly implemented by permutation tables and complex mathematical equations. This paper presents a simple and robust architecture for address generation of deinterleaver used for different wireless communication standards. In order to reduce the silicon cost, hardware multiplexing is introduced. The traditional LUT based address generation is found to be unattractive in many aspects such as large sequential memory requirement, slowness in operation and enormous power consumption. The proposed design is capable of sharing the common hardware between the modules for band phase shift keying (BPSK), quadrature phase-shift keying (QPSK), 16-QAM, and 64-QAM. The algorithm for address generator of the deinterleaver is simplified and simulation results are provided in this paper. This novel technique supports each modulation scheme at different possible code rates. This work uses a finite state machine based architecture to generate addresses which contributes to adequate use of resources. With the increase in bandwidth requirements for communication, it has become necessary to include an address generation technique used for WLAN 802.11n in this work. The comparison between conventional method and proposed technique is made on the basis of power rating and equivalent gate count estimated using Xilinx ISE tool.