Design and VLSI Implementation of N X N Binary Multiplier Using Successive Approximation of (N-1) X (N-1) Binary Multipliers

In VLSI technology, power consumption and delay becomes a major problem in multipliers. To reduce these issues we propose a new multiplier algorithm that combines numerical transformation and shift and add technique. In this design N X N bitmultiplication is done by using successive approximation of (N-1) X (N-1) bit multiplier. The strength of the multiplication is reduced by weight reduction technique. The performance of N-bit multiplier using successive approximation of N-1 bit multiplier is compared with the existing techniques and evaluated through simulation in order to highlight the speed superiority by reducing the number of components and interconnections. N-bit successive approximation is an excellent choice for low area and high speed applications. All the above mentioned multipliers are coded in VHDL and simulated in ModelSim and synthesized in EDA tool Xilinx_ISE 9.2i. This method is suitable for higher order bits. The analysis of power report is also presented here the proposed design is suitable for high speed, low area applications.