Adiabatic Logic Circuits for Low Power VLSI Applications

The power dissipation has become a major design issue in VLSI circuits. As the system size is shrinking gradually it has become one of the prime concerns for the designers. The power dissipation can be reduced by introducing different design techniques. In this paper a new adiabatic approach 2PASCL has been introduced. The power dissipation in adiabatic circuits can be minimized more than 90 % as compared to conventional CMOS logic. In adiabatic circuit the charge stored in load capacitor is recovered while in conventional CMOS it is transferred to ground which causes wastage of energy.