Improvement in the Advanced Encryption Standard Algorithm in Term of Low Area and Power Consumption by using FPGA

In all over the world communication of private and confidential data over the computer networks or the Internet, there is always a chance of the hacking the data from the wrong intention people. Data encryption maintains data privacy and authentication. Information has become of the most important thing in growing demand of have to store every single importance of events in everyday life. Messages have to be secured from unauthorized party. So that encrypts the data. There are two types of encryption algorithms, a private key (symmetric key) and public key. In terms of computational complexity, private key algorithm is not much as complex than a public key algorithm. In this paper implement the AES algorithm on FPGA using VHDL language with using software Xilinx ISE tool. The main target is by maintaining standard throughput of data to achieve low area as well as low power consumption. Also maintain high speed data processing and reduce time for key generating. For an instantaneous output in this paper use BRAM implementation which is alternative to conventional s-box combinational logic. It shows the performance better than other.