Static Power Reduction of a Pulse Enhanced Flip Flop

Flip Flops form an important component of most digital systems today. Flip flops act as the memory elements for many memory chips and microprocessors. Pulse enhancement of the flip flops is done in order to improve their performance and increase the speed. Flip-flop is one of the components of digital systems that consume most of the power due to the presence of clock. As the power budget of today?s portable digital circuit is severely limited. Thus consumption of power needs to be minimized. The major factor contributing in the power consumption is the static power. The situation which has cropped up has made it necessary to devise methods to reduce the static power of a flip flop. This paper presents some methods application of which is expected to significantly reduce the static power. A tradeoff between power and area is required here.