Design of FIR Filter Architecture using Various Efficient Multipliers

Finite impulse response (FIR) filter is one of the important components in any DSP and communication systems. The output from the DSP processor is depends on the FIR filter, so need an efficient FIR filter design, to achieve an efficient output. Filter architecture contains many components; one of the main components is multiplier. Different types of multipliers are available in the digital circuits, but need an efficient multiplier design to get efficient filters. In the existing Wallace tree multiplier was designed and implemented using verilog HDL. This multiplier needs many gates to implement the design. So it takes more area and delay. To reduce the drawbacks in the existing system, to propose a new efficient multiplier named as Birecoder multiplier. It is one of the best multiplier in the digital circuit design. This multiplier overcomes the existing multiplier drawbacks. Multiplier is design by verilogHDL, after the design Wallace tree multiplier is compared with Birecoder, and analyzes the performance of the multiplier. Implement the design using Modelsim 6.3c and Xilinx ISE. Finally the designed multipliers are applied into the FIR filter, and show the best filter. Keywords: Wallace tree, Birecoder, Modelsim 6.3c, Xilinx ISE, FIR filter.