SIMULATION OF ENHANCED PULSE TRIGGERED FLIP FLOP WITH HIGH PERFORMANCE APPLICATIONS

Flip-flops are the major storage elements in all system on chip (SOC) of digital design and one of the most power consumption components. It is important to reduce power dissipation in clock distribution networks and flip-flops. The power delay is mainly due to clock delays. The delay of flip-flops should be minimized for efficient implementation. This paper designed Enhanced Pulse Triggered Flip Flop (D-FF) based different applications (4 bit PIPO, 4bit SISO and 3 bit Asynchronous ripple counter). The design significantly reduces the power dissipation. Performances of all the circuits are investigated power consumption using TSMC 180nm technology.