Design of high speed approximate multipliers with inexact compressor adder

In most practical applications, approximate computation is being used. By using approximate computing, the system performance metrics like area, power and speed can be improved. In this paper an approximate circuit was proposed and developed by modifying the circuit architecture but not the circuit operation. An approximate multiplier using AND-OR logic approximation with Wallace tree reduction, and 3:2 inexact additive designs were proposed for partial product generation and addition. Four different kinds of Approximate Wallace Multiplier (AWM) were implemented using 3:2 compressor adder designs. The concept was discussed, considering an 8×8-bit multiplication as an example. The proposed multipliers achieve substantial improvements in terms of both area and delay. Compared to the conventional multipliers, the AWM1 achieves up to 35.577% reduction in area and 35.224% in delay. AWM2 has an area and delay reductions of up to 48.077% and 36.532% respectively. AWM3 has area savings of up to 48.077% and delay reductions of up to 46.633%. Finally, the AWM4 has area savings of up to 53.846% and delay reductions of up to 56.482%.