PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories

The demand for high-performance electronic gadgets has increased two-folds in the last decade, fueling technology manufacturers to shrink fabrication node sizes. The decreasing channel sizes along with an increase in gate count and cell density pose numerous congestion issues during physical implementation of the chips, making design closure ever more difficult. Double Data Rate (DDR) memories that access data on both edges of the clock cycle require extreme timing control and must meet the strict timing requirements during Physical Design (PD). Floor-plan, being the first stage of back-end PD implementation, is an important step to mitigate congestion and timing issues during the subsequent stages of the implementation. On-chip macros, with connections to the standard cells and the Input/Output (IO) ports of the chip, need to be strategically placed during the floor-plan of the design to enable congestion-free placement of standard cells and signal routes. Previously, designers opted for island macro placement strategy, wherein macros were grouped close together, thereby leaving a uniform square region for standard cell placement. However, this method alone cannot be considered for chip designs today that has denser macro pin connections to the chip IO ports as in the Last Level Cache (LLC) block of a DDR subsystem. In this paper, two new placement strategies have been considered – peripheral and donut, for the LLC module. A congestion-optimized, floor-plan to Place and Route (PNR) flow methodology has been presented for each of these placement strategies using Cadence Innovus Implementation System and Synopsis IC Compiler II. The Quality of Results (QOR) for each strategy was then compared. The peripheral macro placement strategy is found to be best among the three, while the donut macro placement is the worst. A 16% improvement in the overall on-chip delay is seen in the peripheral macro placement when compared to island macro placement. Furthermore, a 19.6% power reduction is observed in the peripheral macro placement strategy as compared to island macro placement. The overall congestion for peripheral macro placement is 0.32%, which is the least among the three strategies. Hence, the peripheral macro placement strategy proves to be the best choice for macro placement, when considering floor-plan for the LLC module in a DDR subsystem.