REVIEW OF DELAY AND POWER EFFICIENT CARRY SELECT ADDER USING PIPELINE

Carry Select Adder (CSLA) is one of the fastest adders which is used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. Current processors are increasing the number of cores to improve the performance. The basic operation of any processor is addition; if we can optimize this operation with minimal hardware increase then it would be a good contribution. The adder circuit is design using VHDL & simulated using Xilinx IES simulator. Multiple instructions are being processed at the same time by using pipeline. This paper presents to improve the system of adder with pipelining technique, as it does not increase the hardware that much, but gives us better speed by using two stages of pipelining to Optimize delay & Power than previously normal carry select adder.