Leakage Reduction Technique for Scan Flip-Flop

Scanning of test vectors during testing causes unnecessary and excessive switching in the combinational circuit compared to that in the normal mode of operation. In proposed system we have created a scan flip-flop based on MTcmos for leakage reduction which eliminates the power consumed due to unnecessary switching in the combinational circuit during scan shift, with a little impact on its performance. Multi-threshold CMOS (MTCMOS) power gating is a design technique in which a power gating transistor is connected between the logic transistors and either power or ground, thus creating a virtual supply rail or virtual ground rail, respectively, the new scan flip-flop by using sleep transistors it will reduce the leakage.