DESIGN AND IMPLEMENTATION OF A HIGHPERFORMANCES NETWORK-ON-CHIP ARCHITECTURE FOR MANY-CORE SYSTEM

As the number of individuals who want access to fast computers continues to rise, computer manufacturers have developed many-core systems that have hundreds or thousands of processors as a response. However, the performance and scalability of the system are limited by the interconnect technology that is used between the cores. Network-on-chip (NoC) designs, which allow scalable and efficient interconnects for many-core systems, offer a potential solution to this challenge and present a realistic way to solving it. The purpose of this work is to present a complete review of current research on the topic of high-performance NoC designs for many-core systems, with a particular emphasis on the design and implementation of these architectures. Several approaches to improving the performance, scalability, energy efficiency, and reliability of NoC systems are explored, along with their advantages, disadvantages, and potential future applications. In addition, the review draws attention to some of the most significant concerns and possible research directions that should be pursued in this area. In conclusion, the review offers light on the current status of the design of NoC architecture and highlights the significance of further research in this rapidly evolving field.