Low Power 16×16 Bit Multiplier Design using Dadda Algorithm

The model of 16 bit multiplier having low power and high speed using Algorithm named Dadda and the basic building block used is optimized Full adder having low power dissipation and minimum propagation delay. Full and half adder blocks have been designed using pass transistor logic and CMOS process technology to reduce the power dissipation and propagation delay. We have also applied Dadda algorithm to reduce the propagation delay. The model has been designed using XILINX. Dr. B. Rambabu | N. Vamsi Krishna | V. Vasavi | Sd. Aftab Biyabani | K. Krishna Prasad "Low Power 16×16 Bit Multiplier Design using Dadda Algorithm" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-7 | Issue-2 , April 2023, URL: https://www.ijtsrd.com.com/papers/ijtsrd53897.pdf Paper URL: https://www.ijtsrd.com.com/engineering/electronics-and-communication-engineering/53897/low-power-16×16-bit-multiplier-design-using-dadda-algorithm/dr-b-rambabu