ELECTRON TRANSPORT IN GRAPHENE BASED NANOTRANSISTOR AND USE OF NEGATIVE CAPACITANCE FOR STEEPER SUB-THRESHOLD SLOPE
Journal: International Journal of Advanced Research (Vol.11, No. 09)Publication Date: 2023-09-19
Authors : Rahul B. Awale;
Page : 766-796
Keywords : Graphene GNRFET Electron Transport Ballistic FET Subthreshold Slope Negative Capacitance;
Abstract
Graphene has demonstrated tremendous promise in recent years as a material that, in the future, could replace silicon-based materials because of its exceptional electrical transfer characteristics. The diffusive MOSFETs suffer from short channel effects caused by their shorter channels, however graphene has numerous unusual features. The strongest material yet tested, Graphene exhibits a significant and nonlinear diamagnetism, has great mobility at room temperature, a low atomic thickness, a high current density, and is almost transparent. A single sheet of carbon atoms organized in a hexagonal lattice makes up graphene, an allotrope form of carbon. It is a semimetal with little short channel effects overall and little overlap between the valence and conduction bands. The Graphene nanoribbon has been incorporated into the ballistic nanotransistor as its channel and differentiate it form the diffusive one.In this review , I have presented the report on the survey of Nanotransistor . It has been divided into three sections : (1) Ballistic transport in Nanotransistor (2) Modelling of GNRFET (Graphene Nano-ribbon FET) using NEGF (Non-equilibrium Greens function) (3) Using ferroelectric capacitance into FET to reduce its sub-threshold regime below 60 mV/decade.The purpose of this review is to understand charge carrier transport phenomenon in the Nanotransistor. This includes the description about the ballistic nanotransister and differentiate it form the diffusive one. The NEGF allows us to characterizing its transfer characteristics in the real lattice space.Also the Id-Vd, sub-threshold regime , log(Id)-Vg , transmission coefficient and their application to drastically enhance the device performance for low energy digital electronics are being studied and modeled. Furthermore, the negative capacitance due to FE (ferroelectric layer) in FET will enhance the switching speed of FET and reduce the sub-threshold swing (SS) below 60 mV/decade which is impossible in case of traditional MOSFET. Thus, improving ION/IOFF ratio for low power digital devices.
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