IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING XILINX WITH VERILOG

This paper presents a 32-bit high-speed Wallace tree multiplier designed using Verilog HDL. The multiplier achieves efficient multiplication by reducing partial products and employs carry-save and ripple carry adders. Practical implementation on FPGA demonstrates its superiority over existing methods in terms of computation time and efficiency. The proposed design addresses the area and speed disadvantages of traditional Wallace tree multipliers, offering a promising solution for high-speed multiplication applications. In this paper a 32-bit high speed Wallace tree multiplier is designed using Verilog and 4-bit multiplication is implemented on Spartan-6 LX45 FPGA and. The entire design of 4-bit multiplication is coded in Verilog HDL, simulated with Modelsim and synthesized using Xilinx FPGA device and the similar algorithm is used for computing 32-bit multiplication. The proposed multiplier is much efficient than the existing methods.