Implementation Of RS Decoder Using High-Speed UHD Architecture

Abstract Reed-Solomon RS codes are widely used as f orward correction codes FEC in digital com munication and storage systems.correcting ran random errors of RS codes have been extensiv ely studied in both academia and industry. Ho wever for burst-error correction the research is still quite limited due to its ultra high compu tation complexity. In this brief starting from a recent theoretical work a low-complexity refo rmulated inversionless burst-error correcting RiBC algorithm is developed for practical ap plications.Then based on the proposed algorit hm a unified VLSI architecture that is capabl e of correcting burst errors as well as random errors and erasures is firstly presented for mu lti-mode decoding requirements. This new arc hitecture is denoted as unified hybrid decoding UHDarchitecture. It will be shown thatbeing the first RS decoder owning enhanced burst er ror correcting capability it can achieve signifi cantly improved error correcting capability th an traditional hard-decision decoding HDD design. A design of 7 3 Reed Solomon encod er and Decoder are implemented using VHDL hardware description language HDL code sim ulated and synthesized by XILINX ISE simulator. General Terms Burst errors Reed-Solomon codesRiBC algorith m and UHD architecture.