SILICON ON INSULATOR TECHNOLOGY REVIEW

An effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. This paper introduces one of the greatest future technologies of this decade and that is SOI technology. Silicon-On-Insulator transistors are fabricated in a small (~100 nm) layer of silicon, located on top of a silicon dioxide layer, called buried oxide. This oxide layer provides full dielectric isolation of the transistor and thus most of the parasitic effects present in bulk silicon transistors are eliminated. The structure of the SOI transistor is depicted and is very similar to that of the bulk transistor. The main difference is the presence of the buried oxide it provides attractive properties to the SOI transistor. Power has become one of the most important paradigms of design convergence for multi gigahertz communication such as optical data links wireless products and microprocessor ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. For more than three decades, scientists have been searching for a way to enhance existing silicon technology to speed up the computer performance. This new success in harnessing SOI technology will result in faster computer chips that also require less power a key requirement for extending the battery life of small, hand-held devices that will be pervasive in the future. SOI is a major breakthrough because it advances chip manufacturing one to two years ahead of conventional bulk silicon. The following provides a step-by-step look at the developments leading up to the development of SOI technology.