VHDL Implementation Of Reconfigurable Crossbar Switch For Binoc Router

Abstract Network-on-Chip NoC is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption area overhead and the entire NoC performance is influenced by the router crossbar switch. This paper presents implementation of 10x10 reconfigurable crossbar switch RCS architecture for Dynamic Self-Reconfigurable BiNoC Architecture for Network On Chip. Its main purpose is to increase the performance flexibility. This paper presents a VHDL based cycle accurate register transfer level model for evaluating the Power and Area of reconfigurable crossbar switch in BiNoC architectures. We implemented a parameterized register transfer level design of reconfigurable crossbar switch RCS architecture. The design is parameterized on i size of packets ii length and width of physical links iii number and depth of arbiters and iv switching technique. The paper discusses in detail the architecture and characterization of the various reconfigurable crossbar switch RCS architecture components. The characterized values were integrated into the VHDL based RTL design to build the cycle accurate performance model. In this paper we show the result of simple 4 x4 as well as 10x10 crossbar switch .The results include VHDL simulation of RCS on ModelSim tool for 4 x4 crossbar switch and Xilinx ISE 13.1 software tool for 10x10 crossbar switch.