DESIGN AND IMPLEMENTATION OF HIGH RELIABLE 6T SRAM CELL

This paper describes a design and implementation of a high reliable 6t SRAM cell with write and read operations. Low - power Random Access Memory (RAM) has seen a remarkable and rapid progress in power reduction. Many circuit techniques for active and standby power reduction in static and dynamic RAMS have been devised but Static random access memory (SRAM) is a critical part of most VLSI system - on - chip (SOC) applications. Conventional SRAM bit cell design consists of 6 transistors. This paper presents a new static random access memory (SRAM) cell with sepa rate write and read circuits. The elementary cell structure of proposed SRAM cell consists of two high load resistors which are constructed of PMOS, and NMOS switch which is necessary to restrict short circuit current.