LOW POWER DESIGN METHODOLOGY FOR ARITHMETIC CIRCUITS

In this paper a modified Constant Delay Logic is been proposed to provide improved performance. Continues scaling in technology of VLSI circuits leads to increase in power consumption. Therefore designing a VLSI circuit technique with low power is a challenging task witho ut sacrificing its performance. The Proposed logic is well suited for the critical path of a low voltage arithmetic circuits which consists of a large number of gates. The modified logic style is examined against the constant delay Logic and feed through l ogic, by analysis through simulation. A 8 - bit ripple carry adder and 32 bit carry look ahead adder are been designed and their performance is evaluated using both proposed logic as well as existing logic designs. It is shown that the modified LP - HS Consta nt Delay Logic has better performance than that of the existing FTL and CDL logics. The simulations were done using HSPICE tool in 32nm, 45nm CMOS technologies with 1v, 1.1v supply voltages respectively