An Efficient Power Saving Latch Based Flip-Flop Design for Low Power Applications

ABSTRACT In Integrated circuits a gargantuan portion of chip power is expended by clocking system which comprises of timing elements such as flip-flops, latches and clock distribution network. This paper enumerates power efficient design of shift registers using D flip-flops along with Clock and Power gating integration. In this paper we shown the Master-Slave design of D-Flip-Flop how we can reduce the number of transistors it the circuit. WE proposed a Latch based Flip-Flop which reduces the Master- Slave Network was shown. These circuits are designed and simulated using Tanner EDA Tools.