Design and Implementation of Equiripple FIR High Pass Filter on FPGA

This paper demonstrates the design and implementation of Equiripple linear-phase FIR high pass filter. The filter is modeled using Simulink in Xilinx System Generator. The filter Coefficients are generated with the help of FDA tools, the SysGen tool is used for RTL code generation. Further the model is used as a filter block to interface with ADC/DAC block in VHDL. The design has been prototyped on Spartan-3 DSP protoboard XC3S500fg320 using Integrated Synthesis Environment (ISE) 13.1 tools all in one design suit from Xilinx. Finally the filter is tested by using an audio signal as input and the output is observed in CRO & speaker both.