AN IMPLEMENTATION OF BYPASSING BASED MULTIPLIER BY USING INCREMENTAL ADDER

In the recent growth of the portable electronics is forcing the designers to optimize the existin g desi gn for better performance . M ultiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. Hence it is very important for modern D SP systems to design h igh speed multipliers. Based on the simplification of ad dition operations in a bypassing multiplier, a multiplier by using incremental adder is proposed. Compared with row bypassing multiplier, column bypassing multiplier and 2 - d imensional bypassing mult iplier, our proposed multiplier reduces the number of computations and increases the speed.