FPGA- IN- THE- LOOP IMPLEMENTATION OF AN ADAPTIVE MATRIX INVERSION ALGORITHMIC CO- PROCESSOR: AN EMBEDDED DUAL- PROCESSOR SYSTEM

This article presents a comprehensive and efficient model- based technique on how algorithms can be developed, synthesized, modeled, pre- verified and implemented on embedded processors platforms which consist of a personal computer and a field programmable gate array (FPGA). To illustrate the proposed technique a new adaptive matrix inversion algorithm is proposed and used. The algorithm is first implemented as a synthesizable streamingloop floating- point MATLAB programs. The MATALAB programs are then synthesized using Xilinx AccelDSP to generate a System Generator block model equivalent of the MATLAB programs. Using the generated System Generator block model, the Xilinx System Generator for DSP is then employed to develop a complete System Generator hardware model of the adaptive matrix inversion algorithm. A FPGA- in- the- loop co- simulation and pre- verification using a generated hardware co- simulation block model is carried out for performance comparison. Next, an embedded MicroBlaze™ processor system is designed, tested and imported into a System Generator hardware model of the adaptive matrix inversion algorithm inside MATLAB/ Simulink environment; and a complete FPGA- in- the- loop implementation is performed. The FPGA- in- the- loop simulation results are presented. Conclusions drawn from the study are given together with some discussions and directions for further work.