Enhanced Key Expansion Algorithm for Advanced Encryption Standard using Different S- Box Implementation on FPGA

The main aim of this paper is encrypt the data using Advanced Encryption Standard (AES) algorithm. In AES algorithm cryptography technique is used. Security is most important in data communication so to increase the security key expansion algorithm is used .In this paper we considering different sizes of S-box to reduce the area and the LUTs. To reduce LUTs here considering the affine transformation method is used. The round key expansion is proposed to improve security against attacks. Encrypted data is decrypted using inverse AES algorithm method .In AES algorithm numbers of round performed during execution will be depended upon the Key length. Here AES -128 bit key are used, so number of round performed during execution will be 10. This algorithm is simulated using Xilinx software and implemented on FPGA.