SIMULATION OF MODIFIED AGC AND PRE?SYNCHRONIZATION PROCESSOR IN LOW POWER SOFTWARE DEFINED RADIO RECEIVER

In this paper, we can conclude that there is a reduction of power consumption by modifying the existing system of software define radio receiver (SDR). From the existing module, the digital front end architecture of SDR contains the two processors known as AGC (Automatic Gain Controller) processor and pre synchronization processors to perform the signal detection and pre synchronization operations. The AGC is used to optimize the ADC range based on the analog front end control things. After the AGC detection, the synchronization operation is done by an application specific processor. In this system, when the sync signal is asserted the digital front end power management can disable the synchronization process and wakeup base band part of the SDR. In the proposed system, the AGC controller and pre synchronization engine processors are integrated into a single processor with different ALUs working for AGC and pre synchronization operations. An ASIC code for detection and synchronization is executed using VLIW processor operation and power management is performed. When AGC is on, the pre synchronization ALU and remaining parts are off. When AGC is completed, the pre synchronization processor is on and AGC is power down. At the end an interrupt is generated to wake up the base band processor. With this, the energy scalable design is achievable and the low power implementation is to be done.