FPGA BASED FIXED POINT LMS ADAPTIVE FILTERS

In this paper, we present an efficient architecture for the implementation of a delayed least mean square adaptive filter. For achieving lower adaptation - delay and area - delay - power efficient implementation, we use a novel partial product generator and propose a strategy for optimized balanced pipelining across the time - consuming combinational blocks of the structure. From synthesis results, we find that the proposed design offers less Area con sumption (Number of Slice) and less delay (Maximum usable Frequency) than the best of the existing systolic structures, on av erage, for filter lengths N = 4, 8, 16 and 32 . The design is Implemented on the FPGA device SPARTAN - 3 (XC3S400 - 5PQ208) and its result is matching with the simulation results for N = 8.