DESIGN OF HIGH SPEED RECONFIGURABLE COPROCESSOR FOR INTERLEAVER AND DE- INTERLEAVER OPERATIONS

In this paper we present the high speed reconfigurable co ?processor for interleaver and de- interleaver system. Today’s communications systems have to perform in the midst of extreme signal, complex depth and diversity .With help of reconfigurable co-processor we can ensure the communications systems are ready for next generation operations . The communication system commonly uses an interleaver and de-interleaver tec hnique for security purpose to overcome burst error such as correlated channel noise and authenti cation. The proposed reconfigurable co-processor for interleaver and de-interleaver is more accurate , reliable and flexible.