VHDL MODELING OF THE SRAM MODULE AND STATE MACHINE CONTROLLER (SMC) MODULE OF RC4 STREAM CIPHER ALGORITHM FOR Wi-Fi ENCRYPTION
Journal: International Journal of Electronics and Communication Engineering and Technology (IJECET) (Vol.6, No. 1)Publication Date: 2015-01-30
Authors : Dr.A.M. BHAVIKATTI; MALLIKARJUN.MUGALI;
Page : 79-85
Keywords : VHDL simulation; RC4 streamcipher; SRAM module; State machine diagram; Iaeme Publication; IAEME; Communication; Engineering; IJECET;
Abstract
In this paper, VHDL modeling of the SRAM module and State Machine Controller (SMC) module of RC4 stream cipher algorithm for Wi-Fi encryption is proposed. Various individual modules of Wi-Fi security have been designed, verified functionally using VHDL-simulator. In cryptography RC4 is the most widely used software stream cipher and is used in popular protocols such as Transport Layer Security (TLS) (to protect Internet traffic) and WEP (to secure wireless networks). While remarkable for its simplicity and speed in software, RC4 has weaknesses that argue against its use in new systems. It is especially vulnerable when the beginning of the output key stream is not discarded, or when nonrandom or related key s are used; some ways of using RC4 can lead to very insecure cryptosystems such as WEP .
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